The present invention generally relates to semiconductor integrated circuit technology and, more particularly, to a process for electroplating on a workpiece.
In IC fabrication, formation of wiring networks on the ICs often presents technological problems. In particular, certain applications require formation of both narrow wires or other structures and wide wires, electrodes, bond pads or other structures, with the narrow and wide structures adjacent to one another and as closely spaced as allowed. Such conductive networks require forming narrow and large gaps through a mask layer, which is typically a photoresist layer, coated on a substrate and filling them with a conductive material such as copper.
As exemplified in FIG. 1, in one conventional process, an upper surface 9 of a silicon or device substrate 10 is first coated with a barrier layer 12 and then with a copper seed layer 14. It should be noted that the substrate 10 typically contains more layers of metal interconnect structures, insulators and devices below the upper surface 9, which are not shown in detail in FIG. 1. The barrier layer 12 helps adhesion of copper to the upper surface 9 and also serves as a diffusion barrier for copper. The barrier layer 12 is typically made of a single or multilayer films, such as Ta, TaN, Cr, TiW, NiP, TaN/Ta, WC, WN, WNC, Al/Nixe2x80x94V, carbon and nitrogen doped tungsten or even, Ti/Cu/Ni layer and their various combinations. In Ti/Cu/Ni, Ti is for adhesion and sealing, Cu for current conduction and Ni serves as the diffusion barrier and wettable layer. In some other applications a dewetting layer or surface or region may also be incorporated. The seed layer 14 may be a thin film copper, or copper alloy, silver or silver alloy layer that provides a base layer on which better nucleation and growth of the subsequently deposited metal layer can take place. A resist layer 16 is formed on the seed layer 14 and defined and etched to form various features by lithographic processes. The resist material may be soft or hard baked organic materials, it could be inorganic materials such as silicon oxide, alumina or even sapphire. The resist material may also be a low or high dielectric constant material. In this invention, a resist material is a material that copper or any metal of interest will not substantially nucleate on without a seed layer coating. In FIGS. 1 and 2A two exemplary features etched in the resist, a narrow line or via 18 and a wider structure such as a trench or a via 20 are shown with the seed layer in exposed portions 24 on the bottom of these features. These features require filling with copper.
Filling up such features with copper with the conventional electroplating processes from additive or additive free baths, present problems. As shown in FIG. 2A, as copper layer 22 grows on exposed portions 24 of the seed layer to fill the features from bottom to top, wider features or trenches 20 may fill up before narrower features or lines 18. As seen in FIG. 2A, at time t1, although the wide trench 20 is already filled, the narrow line 18 is only partially filled. As the electroplating time is extended until time t2 in order to fill the narrow line 18, the wide trench 20 is overfilled and a copper dome 26 may form on the wide trench 20 due to the extra electroplating time.
Such filling discrepancies between features of various shapes and sizes may be due to various reasons such as differences in mass transfer of the plating electrolyte into features with different aspect ratios, the location of the features with respect to high current density regions such as contacts, and location of different size features with respect to each other. For example, apart from concerns about nonuniform electric field distribution across the workpiece, mass transfer is not as efficient in small features as in large features. Therefore, current densities tend to be higher in larger features. If a small and large feature are side by side and their size difference is high, the large feature may steal current density from the small one resulting in the phenomenon depicted in FIG. 2A.
Further, in IC design, if the larger feature density is higher on certain regions of the IC, the severity of this problem becomes higher in such regions. As is apparent, taking into account such factors limit the most efficient circuit layout in terms of electrical circuit performance. This is particularly true since rigid design rules also need to be followed. For instance, all vias may be essentially the same diameter according to the specified design rules, and their minimum spacing from each other may also be specified by the design rules, such as being at least xc2xc of their diameter to prevent shorting and the like. Such design rules, while necessary using conventional process technologies, nonetheless result in a loss of flexibility in wiring design and layout, thereby causing losses in wiring densities, but also resulting in performance penalties and the inability to integrate certain functionalities in a package or wafer. For example, it may result in passive and active electrical elements, or the leads thereto, not being capable of being integrated in close proximity to each other. One aspect of this reduced flexibility is that many wide features cannot be fabricated in very close to very narrow lines, as mentioned above. Many very fine lines or features, for example those less than 5 microns in width, cannot be readily attached to very wide lines, vias or features larger than, for example, 20 microns, without incurring severe cost penalties.
If the various features, regardless of dimensions, shape, locations or relative locations on a workpiece could be filled up in a uniform manner at the same rate, many of the problems discussed above would be overcome.
As discussed above, conventional copper deposition methods yield a copper structure that is very non-uniform, i.e., some features are overfilled at the expense of others. The overfilled extra copper needs to be subsequently removed using material removal techniques such as chemical mechanical polishing (CMP) process. These material removal techniques are complicated and costly, and even more costly, especially when a thick layer of the conductive material is to be planarized.
Conventionally, after the metal deposition, the resist layer 16, and the seed layer 14 and barrier layer portions disposed below the resist layer are removed to isolate the various electrical structures of interest, as shown in FIG. 2B. The large disparity in the height of large structure and smaller one is obvious in the absence of the masking resist layer. The height H1 of the copper structure 22a is significantly greater than H2 of the copper structure 22b. After seed layer and barrier layer removal, the difference between the small and the large features becomes even more significant. The seed layer thickness is nearly insignificant when compared to the width X1 and height H1 of structure 22a. Because the removal process can affect all of the conductors, it can affect all structures, not only the seed layer and barrier layer portions being removed. Thus removal of the seed layer portions does not significantly affect the structure 22a, in terms of the desired width X12 and height H12 in FIG. 2C, which shows the structures after the removal of the seed and barrier layer portions. The seed layer portion removal, however, may be catastrophic for finer features such as the structure 22b as shown by the significantly reduced size of the structure 22b that has been affected by the removal process. Mass transfers and surface area effects cooperate during seed layer removal to produce an undesirable structure, especially with respect to the height H22 of the structure 22b. The large difference xe2x80x98xcex94Hxe2x80x99 between the heights of two structures of differing sizes also represents a severe design rule violation. This is another fundamental reason that limits the choice of pattern geometries and their layouts in many device designs employing thru-mask plating processes.
To this end, there is a need for development of a thru-mask plating technology that eliminates the strict limits imposed by the conventional plating methods.
The present inventions provide methods and apparatus to enable thru-mask contact electrodeposition without the disadvantages suffered by conventional thru-mask deposition methods.
In one aspect of the present invention, a process for forming a conductive structure on a substrate is provided. The substrate has a metal seed layer that is partially exposed through a plurality of openings in a masking layer such as a photoresist. The masking layer is formed on the seed layer. The process electroplates copper through the openings and onto the seed layer. During the copper electroplating process the surface of the masking layer is mechanically swept. The process forms planar conductive material deposits filling the plurality of holes in the masking layer. The upper ends of the conductive deposits are substantially co-planar
In particular, the present inventions minimize mass transfer of material to certain features once they are filled, while continuing to allow mass transfer of material to other features that have not yet filled, when depositing on workpiece surfaces that have an insulator such as a resist over certain top surfaces of the workpiece.